10.5.11 ADCPSSI Register (Offset = 0x28) [reset = X]
ADC Processor Sample Sequence Initiate (ADCPSSI)
This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC modules. To do this, the first ADC module should be configured. The ADCPSSI register for that module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit. Additional ADC modules should then be configured following the same procedure. Once the final ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their configuration.
ADCPSSI is shown in Figure 10-25 and described in Table 10-18.
Return to Summary Table.
Figure 10-25 ADCPSSI Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| GSYNC |
RESERVED |
SYNCWAIT |
RESERVED |
| R/W-X |
R-0x0 |
R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SS3 |
SS2 |
SS1 |
SS0 |
| R-0x0 |
W-X |
W-X |
W-X |
W-X |
|
Table 10-18 ADCPSSI Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
GSYNC |
R/W |
X |
Global Synchronize.
0x0 = This bit is cleared once sampling has been initiated.
0x1 = This bit initiates sampling in multiple ADC modules at the same time. Any ADC module that has been initialized by setting an SSn bit and the SYNCWAIT bit starts sampling once this bit is written.
|
| 30-28 |
RESERVED |
R |
0x0 |
|
| 27 |
SYNCWAIT |
R/W |
0x0 |
Synchronize Wait.
0x0 = Sampling begins when a sample sequence has been initiated.
0x1 = This bit allows the sample sequences to be initiated, but delays sampling until the GSYNC bit is set.
|
| 26-4 |
RESERVED |
R |
0x0 |
|
| 3 |
SS3 |
W |
X |
SS3 Initiate.
Only a write by software is valid
a read of this register returns no meaningful data.
0x0 = No effect
0x1 = Begin sampling on Sample Sequencer 3, if the sequencer is enabled in the ADCACTSS register.
|
| 2 |
SS2 |
W |
X |
SS2 Initiate.
Only a write by software is valid
a read of this register returns no meaningful data.
0x0 = No effect
0x1 = Begin sampling on Sample Sequencer 2, if the sequencer is enabled in the ADCACTSS register.
|
| 1 |
SS1 |
W |
X |
SS1 Initiate.
Only a write by software is valid
a read of this register returns no meaningful data.
0x0 = No effect
0x1 = Begin sampling on Sample Sequencer 1, if the sequencer is enabled in the ADCACTSS register.
|
| 0 |
SS0 |
W |
X |
SS0 Initiate.
Only a write by software is valid
a read of this register returns no meaningful data.
0x0 = No effect
0x1 = Begin sampling on Sample Sequencer 0, if the sequencer is enabled in the ADCACTSS register.
|