10.5.7 ADCUSTAT Register (Offset = 0x18) [reset = 0x0]
ADC Underflow Status (ADCUSTAT)
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position.
ADCUSTAT is shown in Figure 10-21 and described in Table 10-14.
Return to Summary Table.
Figure 10-21 ADCUSTAT Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
UV3 |
UV2 |
UV1 |
UV0 |
| R-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
|
Table 10-14 ADCUSTAT Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
UV3 |
R/W1C |
0x0 |
SS3 FIFO Underflow.
The valid configurations for this field are shown below.
This bit is cleared by writing a 1.
0x0 = The FIFO has not underflowed.
0x1 = The FIFO for the Sample Sequencer has hit an underflow condition, meaning that the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned.
|
| 2 |
UV2 |
R/W1C |
0x0 |
SS2 FIFO Underflow.
The valid configurations are the same as those for the UV3 field.
This bit is cleared by writing a 1. |
| 1 |
UV1 |
R/W1C |
0x0 |
SS1 FIFO Underflow.
The valid configurations are the same as those for the UV3 field.
This bit is cleared by writing a 1. |
| 0 |
UV0 |
R/W1C |
0x0 |
SS0 FIFO Underflow.
The valid configurations are the same as those for the UV3 field.
This bit is cleared by writing a 1. |