SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
CAN Message 1 Valid (CANMSG1VAL), offset 0x160
CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects. By reading these bits, the CPU can check which message object is valid. The message valid bit of a specific message object can be changed with the CANIFnARB2 register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in the message RAM.
CANMSGnVAL is shown in Figure 11-23 and described in Table 11-26.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSGVAL | ||||||||||||||||||||||||||||||
R-0x0 | R-0x0 | ||||||||||||||||||||||||||||||