SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In deep-sleep mode, the clock frequency of the active peripherals may change (depending on the deep-sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the microcontroller to run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-sleep mode is entered by first setting the SLEEPDEEP bit in the System Control (SYSCTRL) register and then executing a WFI instruction. Any properly configured interrupt event in the system returns the processor to run mode. See Section 1.8 for more details.
NOTE
If the DAP is enabled in run mode and the device tries to transition into deep-sleep mode, the device is prevented from entering deep-sleep mode.
The Cortex-M4F processor core and the memory subsystem are not clocked in deep-sleep mode. Peripherals are clocked if enabled in the peripheral-specific DCGC registers when automatic clock gating is enabled or in the peripheral-specific RCGC registers when automatic clock gating is disabled.
The system clock source is specified in the DSCLKCFG register. When the DSCLKCFG register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware shuts down the PLL for power savings. For additional power savings, the PIOSC can be disabled through the PIOSCPD bit in the DSCLKCFG register. When the deep-sleep exit event occurs, hardware returns the system clock to the source and frequency it had at the start of deep-sleep mode before enabling the clocks that had been stopped during deep-sleep mode. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during deep-sleep mode (see Section 4.2.14).
NOTE
If the MOSC is chosen as the deep-sleep clock source in the DSCLKCFG register, the MOSC must also be configured as the run and sleep clock source in the RSCLKCFG register before entering deep-sleep mode. If the PIOSC, LFIOSC, or Hibernation RTC module oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the run and sleep clock source in the RSCLKFCFG register, and the MOSC is configured as the deep-sleep clock source in the DSCLKCFG register, then two outcomes are possible:
To provide the lowest possible deep-sleep power consumption and the ability to wake the processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the communications modules have a clock control register at offset 0xFC8 in the module register space. The CS field in the clock control register lets the user select the PIOSC or ALTCLK as the clock source for the baud clock of the module. When the microcontroller enters deep-sleep mode, the PIOSC or ALTCLK becomes the source for the module clock as well, which allows the transmit and receive FIFOs to continue operation while the microcontroller is in deep-sleep mode. Figure 4-6 shows how the clocks are selected.
Additional power-management modes are available that lower the power consumption of the peripheral memory, flash memory, and SRAM. However, the lower power consumption modes have slower deep-sleep and wake-up times.
NOTE
If one or more wait states are configured for run mode, when the device enters deep-sleep mode, it achieves its lowest possible current. If no wait states are applied in run mode, the lowest possible current is not achieved.