15.5.1.1 Default Configuration
To enable the Ethernet PHY with its default configuration, the steps are as follows:
- To hold the Ethernet PHY from transmitting energy on the line during configuration, set the PHYHOLD bit to 1 in the EMACPC register.
- Enable the clock to the PHY module by writing 0x0000.0001 to the Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY) register at offset 0x630. When the R0 bit reads as 1 in the PREPHY register at System Control offset 0xA30, continue initialization.
- Enable power to the Ethernet PHY by setting the P0 bit in the PCEPHY register at System Control offset 0x930. When the R0 bit reads as 1 in the PREPHY register at System Control offset 0xA30, the PHY registers are ready for programming.