SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, thus the base address is n/a (not applicable). The offset for the channel control structures is the offset from the entry in the channel control table.
The µDMA Channel Control Structure holds the transfer settings for a µDMA channel. Each channel has two control structures, which are located in a table in system memory. See Section 8.3.4 for an explanation of the Channel Control Table and the Channel Control Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
Table 8-18 lists the memory-mapped registers for the µDMA Channel Control Structure.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | DMASRCENDP | DMA Channel Source Address End Pointer | Section 8.5.1 |
| 0x4 | DMADSTENDP | DMA Channel Destination Address End Pointer | Section 8.5.2 |
| 0x8 | DMACHCTL | DMA Channel Control Word | Section 8.5.3 |
Complex bit access types are encoded to fit into small table cells. Table 8-13 lists the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |