| 31-30 |
RESERVED |
R |
0x0 |
|
| 29 |
TT |
R |
0x0 |
Timestamp Trigger Interrupt Status. Software can read the Ethernet MAC Timestamp Status (EMACTIMSTAT) register for the exact cause of interrupt and clear its source to reset this bit to 0. When this bit is 1, the interrupt signal from the MAC subsystem is high.
0x0 = No Timestamp interrupt has occurred.
0x1 = An interrupt event in the Timestamp module has occurred.
|
| 28 |
PMT |
R |
0x0 |
MAC PMT Interrupt Status. Software can read the PMT Control and Status (EMACPMTCTLSTAT) register for the exact cause of the interrupt and clear its source to reset this bit to 0. When this bit is 1, the interrupt signal from the MAC subsystem is high.
0x0 = No PMT interrupt has occurred.
0x1 = An interrupt event in the PMT module has occurred.
|
| 27 |
MMC |
R |
0x0 |
MAC MMC Interrupt. This bit reflects an interrupt event in the MMC module. Software must read the corresponding EMACMMCTXRIS/EMACMMCRXRIS register to determine the cause of the interrupt and then clear its source to reset this bit to 0.
0x0 = No MMC interrupt has occurred.
0x1 = An interrupt in the MMC module has occurred.
|
| 26 |
RESERVED |
R |
0x0 |
|
| 25-23 |
AE |
R |
0x0 |
Access Error. This field indicates the type of error that caused a bus error, for example, error response on the internal bus interface. This field is valid only when bit[13] (FBI) is set. This field does not generate an interrupt.
0x0 = Error during RX DMA Write Data Transfer
0x1 = Reserved
0x2 = Reserved
0x3 = Error during TX DMA Read Data Transfer
0x4 = Error during RX DMA Descriptor Write Access
0x5 = Error during TX DMA Descriptor Write Access
0x6 = Error during RX DMA Descriptor Read Access
0x7 = Error during TX DMA Descriptor Read Access
|
| 22-20 |
TS |
R |
0x0 |
Transmit Process State. This field indicates the Transmit DMA state. This field does not generate an interrupt.
0x0 = Stopped; Reset or Stop transmit command processed
0x1 = Running; Fetching transmit transfer descriptor
0x2 = Running; Waiting for status
0x3 = Running; Reading data from host memory buffer and queuing it to transmit buffer (TX FIFO)
0x4 = Writing Timestamp
0x5 = Reserved
0x6 = Suspended; Transmit descriptor unavailable or transmit buffer underflow
0x7 = Running; Closing transmit descriptor
|
| 19-17 |
RS |
R |
0x0 |
Received Process State. This field indicates the Receive DMA state. This field does not generate an interrupt.
0x0 = Stopped: Reset or stop receive command issued
0x1 = Running: Fetching receive transfer descriptor
0x2 = Reserved
0x3 = Running: Waiting for receive packet
0x4 = Suspended: Receive descriptor unavailable
0x5 = Running: Closing receive descriptor
0x6 = Writing Timestamp
0x7 = Running: Transferring the receive packet data from receive buffer to host memory
|
| 16 |
NIS |
R/W1C |
0x0 |
Normal Interrupt Summary.
Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in EMACDMAIM register:
- EMACDMARIS register, bit [0]: Transmit Interrupt
- EMACDMARIS register, bit[2]: Transmit Buffer Unavailable
- EMACDMARIS register, bit[6]: Receive Interrupt
- EMACDMARIS register, bit[14]: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in the EMACDMAIM register) affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared.
|
| 15 |
AIS |
R/W1C |
0x0 |
Abnormal Interrupt Summary.
Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the EMACDMAIM register:
- EMACDMARIS register, bit[1]: Transmit Process Stopped
- EMACDMARIS register, bit[3]: Transmit Jabber Timeout
- EMACDMARIS register, bit[4]: Receive FIFO Overflow
- EMACDMARIS register, bit[5]: Transmit Underflow
- EMACDMARIS register, bit[7]: Receive Buffer Unavailable
- EMACDMARIS register, bit[8]: Receive Process Stopped
- EMACDMARIS register, bit[9]: Receive Watchdog Timeout
- EMACDMARIS register, bit[10]: Early Transmit Interrupt
- EMACDMARIS register, bit[13]: Fatal Bus Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This bit must be cleared each time a corresponding bit, which causes AIS to be set, is cleared.
|
| 14 |
ERI |
R/W1C |
0x0 |
Early Receive Interrupt.
0x0 = No early receive event has occurred.
0x1 = The DMA has filled the first data buffer of the packet. This bit is cleared when software writes a 1 to this bit or if bit[6] (RI) of this register is set.
|
| 13 |
FBI |
R/W1C |
0x0 |
Fatal Bus Error Interrupt.
0x0 = No bus error has occurred.
0x1 = A bus error has occurred, as described in the Error Bit field (EB [25:23]). When this bit is set, the corresponding DMA engine disables all of its bus accesses.This bit is cleared by writing a 1 to it.
|
| 12-11 |
RESERVED |
R |
0x0 |
|
| 10 |
ETI |
R/W1C |
0x0 |
Early Transmit Interrupt.
0x0 = No early transmit has occurred.
0x1 = A frame to be transmitted has been fully transferred to the TX/RX Controller Transmit FIFO.This bit is cleared by writing a 1 to it.
|
| 9 |
RWT |
R/W1C |
0x0 |
Receive Watchdog Time-out.
0x0 = No watchdog time-out event has occurred.
0x1 = Indicates a frame with length greater than 2,048 bytes is received (10, 240 when Jumbo Frame mode is enabled).This bit is cleared by writing a 1 to it.
|
| 8 |
RPS |
R/W1C |
0x0 |
Receive Process Stopped.
0x0 = No receive process stopped event has occurred.
0x1 = Indicates the receive process has entered the stopped state.This bit is cleared by writing a 1 to it.
|
| 7 |
RU |
R/W1C |
0x0 |
Receive Buffer Unavailable. To resume processing receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the receive process resumes when the next recognized incoming frame is received. This bit is set only when the previous receive descriptor is owned by the DMA.
0x0 = No receive buffer unavailable event has occurred.
0x1 = Indicates the host owns the next descriptor in the receive list and the DMA cannot acquire it. The receive process is suspended.This bit is cleared by writing a 1 to it.
|
| 6 |
RI |
R/W1C |
0x0 |
Receive Interrupt.
0x0 = No frame reception complete event has occurred.
0x1 = A frame reception is complete. When reception is complete, bit[31] of RDES1 (disable interrupt on completion) is reset in the last descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state.This bit is cleared by writing a 1 to it.
|
| 5 |
UNF |
R/W1C |
0x0 |
Transmit Underflow.
0x0 = No transmit underflow event has occurred.
0x1 = Indicates the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.This bit is cleared by writing a 1 to it.
|
| 4 |
OVF |
R/W1C |
0x0 |
Receive Overflow.
0x0 = No receive overflow event has occurred.
0x1 = The receive buffer had an overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11].This bit is cleared by writing a 1 to it.
|
| 3 |
TJT |
R/W1C |
0x0 |
Transmit Jabber Time-out.
0x0 = No transmit jabber time-out event has occurred.
0x1 = The Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when Jumbo frame is enabled).When the Jabber Time-out occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Time-out TDES0[14] flag to assert.This bit is cleared by writing a 1 to it.
|
| 2 |
TU |
R/W1C |
0x0 |
Transmit Buffer Unavailable. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command.
0x0 = No transmit buffer unavailable event has occurred.
0x1 = Indicates the host owns the next descriptor in the transmit list and the DMA cannot acquire it. Transmission is suspended. The transmit process state bits (TS [22:20]) explain the transmit process state transitions.This bit is cleared by writing a 1 to it.
|
| 1 |
TPS |
R/W1C |
0x0 |
Transmit Process Stopped.
0x0 = Interrupt is inactive.
0x1 = Indicates transmission is stopped.
|
| 0 |
TI |
R/W1C |
0x0 |
Transmit Interrupt. This bit indicates that frame transmission is complete. When transmission is complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in the first descriptor, and the specific frame status information is updated in the descriptor.
0x0 = Frame transmission completion event has not occurred.
0x1 = Frame transmission is complete.This bit is cleared by writing a 1 to it.
|