| 31-16 |
PT |
R/W |
0x0 |
Pause Time. This field holds the value to be used in the pause time field in the transmit control frame. For example, if these bits are set to 0x0100 then 256 slot times are used in the Pause Time field in the transmit control frame.
|
| 15-8 |
RESERVED |
R |
0x0 |
|
| 7 |
DZQP |
R/W |
0x0 |
Disable Zero-Quanta Pause. When this bit is set, it disables the automatic generation of the Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled.
0x0 = Automatic Zero-Quanta Pause Control generation is enabled.
0x1 = Automatic Zero-Quanta Pause Control generation is disabled.
|
| 6-4 |
RESERVED |
R |
0x0 |
|
| 3 |
UP |
R/W |
0x0 |
Unicast Pause Frame Detect.
0x0 = MAC detects only a Pause frame with the unique multicast address specified in the 802.3x standard.
0x1 = The MAC detects the pause frames with the station's unicast address specified in the EMACADDR0H and EMACADDR0L register, in addition to detecting pause frames with the unique multicast address.
|
| 2 |
RFE |
R/W |
0x0 |
Receive Flow Control Enable.
0x0 = The decode function of the pause frame is disabled.
0x1 = The MAC decodes the received pause frame and disables its transmitter for a specified (pause) time.
|
| 1 |
TFE |
R/W |
0x0 |
Transmit Flow Control Enable.
0x0 = In full duplex mode, the flow control operation in the MAC is disabled, and the MAC does not transmit any pause frames.In half duplex mode, the back-pressure feature is disabled.
0x1 = In the full-duplex mode, the MAC enables the flow control operation to transmit pause frames.In half-duplex mode, the MAC enables the back-pressure operation.
|
| 0 |
FCBBPA |
R/W |
0x0 |
Flow Control Busy or Back-pressure Activate. In the full-duplex mode, this bit should be read as 0x0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 0x1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC resets this bit to 0x0. The EMACFLOWCTL register should not be written to until this bit is cleared.
0x0 = No effect
0x1 = In the full-duplex mode, a pause control frame is enabled. In half-duplex mode, a back-pressure function is enabled if the TFE bit is set.
|