SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet MAC Memory Power Control (EMACMPC)
This register provides power control to the peripheral memory array.
NOTE
The EMAC memory array does not support retention and can only be turned on and off. Memory array off is supported only when the power domain is off. If the memory array is turned on (PWRCTL = 0x3) and the power control to the EMAC is removed by clearing the P0 bit of the PCEMAC register, the memory array is turned off and the MEMSTAT bit in the EMACPDS register is 0x0.
EMACMPC is shown in Figure 4-41 and described in Table 4-48.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRCTL | ||||||||||||||
R-0x0 | R/W-0x3 | ||||||||||||||