15.6.68 EMACPP Register (Offset = 0xFC0) [reset = 0x103]
Ethernet MAC Peripheral Property Register (EMACPP)
This register defines the Ethernet MAC and PHY type used.
EMACPP is shown in Figure 15-83 and described in Table 15-93.
Return to Summary Table.
Figure 15-83 EMACPP Register
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
RESERVED |
R-0x0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
MACTYPE |
RESERVED |
PHYTYPE |
R-0x0 |
R-0x1 |
R-0x0 |
R-0x3 |
|
Table 15-93 EMACPP Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
31-11 |
RESERVED |
R |
0x0 |
|
10-8 |
MACTYPE |
R |
0x1 |
Ethernet MAC Type.
0x0 = Reserved
0x1 = MSP432E4 class MAC.
0x2 = Reserved
0x3 = Reserved
0x4 = Reserved
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved
|
7-3 |
RESERVED |
R |
0x0 |
|
2-0 |
PHYTYPE |
R |
0x3 |
Ethernet PHY Type. This field specifies the type of PHY provided.
0x0 = Reserved
0x1 = Reserved
0x2 = Reserved
0x3 = MSP432E4 class PHY
0x4 = Reserved
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved
|