SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
NOTE
The JTAG controller can be reset by a POR or by holding the TMS pin high for 5 clock cycles.
During an externally generated POR, the internal POR circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VPOR). Reset does not complete if specific voltage parameters are not met as defined in the device-specific data sheet. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in Section 4.1.2.4. Holding this pin active can keep the initialization process from starting even though a POR has occurred. This is useful for in-circuit testing and other situations where it is desirable to delay the operation of the device until an external supervisor has released.
The POR sequence is:
The internal POR is active only on the initial power-up of the microcontroller, when the microcontroller wakes from hibernation, and when the VDD supply drops below the its defined operating limit. See the device-specific data sheet for information on exact values.