SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
FIFO peripherals contain a FIFO of data to be sent and a FIFO of data that has been received. The µDMA controller is used to transfer data between these FIFOs and system memory. For example, when a UART FIFO contains one or more entries, a single transfer request is sent to the µDMA for processing. If this request has not been processed and the UART FIFO reaches the interrupt FIFO level set in the UART Interrupt FIFO Level Select (UARTIFLS) register, another interrupt is sent to the µDMA which is higher priority than the single-transfer request. In this instance, an ARBSIZ transfer is performed as configured in the DMACHCTL register. After the transfer is complete, the DMA sends a receive or transmit complete interrupt to the UART Raw Interrupt Status (UARTRIS) register.
If the FIFO peripheral's SETn bit is set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register, then the µDMA only performs transfers defined by the ARBSIZ bit field in the DMACHCTL register for better bus utilization. For peripherals that tend to transmit and receive in bursts, such as the UART, TI recommends against the use of this configuration, because it could cause the end of transmissions to stick in the FIFO.