SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The EPI controller provides a glueless, programmable interface to a variety of common external peripherals such as SDRAM x16, host bus x8 and x16 devices, RAM, NOR flash memory, CPLDs, and FPGAs. In addition, the EPI controller provides custom GPIOs that can provide a fast speed-controlled parallel interface using either the internal write FIFO (WFIFO) or the nonblocking read FIFO (NBRFIFO) based on the amount of data in the FIFO.
The WFIFO can hold four words of data that are written to the external interface at the rate controlled by the EPI Main Baud Rate (EPIBAUD) registers. The NBRFIFO can hold 8 words of data and samples at the rate controlled by the EPIBAUD register. The EPI controller provides predictable operation and thus has an advantage over regular GPIOs, which have more variable timing due to on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction completes. Nonblocking reads are performed in the background and allow the processor to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no stalls.
NOTE
Poll both the WTAV bit field in the EPIWFIFOCNT register and the WBUSY bit in the EPISTAT register to determine if there is a current write transaction from the WFIFO. If both of these bits are clear, then a new bus access may begin.
Main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xDFFF.FFFF. A read from an address-mapped location uses the offset and size to control the address and size of the external operation. When performing a multiple-value load, the read is done as a burst (when available) to maximize performance. A write to an address-mapped location uses the offset and size to control the address and size of the external operation. When performing a multiple-value store, the write is done as a burst (when available) to maximize performance.