SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pullup resistors (PUE[3:0] set in the Port C GPIO Pullup Select (GPIOPUR) register), disabling the pulldown resistors (PDE[3:0] cleared in the Port C GPIO Pulldown Select (GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select (GPIOAFSEL) register) on the JTAG/SWD pins. See Section 17.5.10, Section 17.5.15, Section 17.5.16, and Section 17.5.18.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design.
NOTE
It is possible to create a software sequence that prevents the debugger from connecting to the MSP432E4 microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the MSP432E4 flash programmer "Unlock" feature.
The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and the NMI pin (see for pin numbers). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see Section 17.5.10), GPIO Pullup Select (GPIOPUR) register (seeSection 17.5.15), GPIO Pulldown Select (GPIOPDR) register (see Section 17.5.16), and GPIO Digital Enable (GPIODEN) register (see Section 17.5.18) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (seeSection 17.5.19) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see Section 17.5.20) have been set.