| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-13 |
TCACT |
R/W |
0x0 |
Timer Compare Action Select.
0x0 = Disable compare operations
0x1 = Toggle State on Time-Out
0x2 = Clear CCP on Time-Out
0x3 = Set CCP on Time-Out
0x4 = Set CCP immediately and toggle on Time-Out
0x5 = Clear CCP immediately and toggle on Time-Out
0x6 = Set CCP immediately and clear on Time-Out
0x7 = Clear CCP immediately and set on Time-Out
|
| 12 |
TBCINTD |
R/W |
0x0 |
One-Shot/Periodic Interrupt Disable.
0x0 = Time-out interrupt functions normally
0x1 = Time-out interrupt functionality is disabledSetting the TBCINTD bit in the GPTMTBMR register does not have an effect on the µDMA or ADC interrupt time-out event trigger assertions. If the TBTODMAEN bit is set in the GPTMDMAEV register or the TBTOADCEN bit is set in the GPTMADCEV register, a µDMA or ADC time-out trigger is sent to the µDMA or ADC, respectively, even if the TBCINTD bit is set.
|
| 11 |
TBPLO |
R/W |
0x0 |
GPTM Timer B PWM Legacy Operation.
This bit is only valid in PWM mode.
0x0 = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0.
0x1 = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0.
|
| 10 |
TBMRSU |
R/W |
0x0 |
GPTM Timer B Match Register Update.
If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBMATCHR and GPTMTBPR are updated when the timer is enabled.
If the timer is stalled (TBSTALL is set), GPTMTBMATCHR and GPTMTBPR are updated according to the configuration of this bit.
0x0 = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next cycle.
0x1 = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next timeout.
|
| 9 |
TBPWMIE |
R/W |
0x0 |
GPTM Timer B PWM Interrupt Enable.
This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output as defined by the TBEVENT field in the GPTMCTL register.
In addition, when this bit is set and a capture event occurs, Timer B automatically generates triggers to the ADC and DMA if the trigger capability is enabled by setting the TBOTE bit in the GPTMCTL register and the CBEDMAEN bit in the GPTMDMAEV register, respectively.
This bit is only valid in PWM mode.
0x0 = Capture event interrupt is disabled.
0x1 = Capture event is enabled.
|
| 8 |
TBILD |
R/W |
0x0 |
GPTM Timer B Interval Load Write.
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running.
If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR, GPTMTBV and are updated when the timer is enabled.
If the timer is stalled (TBSTALL is set), GPTMTBR and GPTMTBPS are updated according to the configuration of this bit.
0x0 = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next cycle. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next cycle.
0x1 = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next timeout. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next timeout.
|
| 7 |
TBSNAPS |
R/W |
0x0 |
GPTM Timer B Snap-Shot Mode.
0x0 = Snap-shot mode is disabled.
0x1 = If Timer B is configured in the periodic mode, the actual free-running value of Timer B is loaded at the time-out event into the GPTM Timer B (GPTMTBR) register. If the timer prescaler is used, the prescaler snapshot is loaded into the GPTM Timer B (GPTMTBPR).
|
| 6 |
TBWOT |
R/W |
0x0 |
GPTM Timer B Wait-on-Trigger.
0x0 = Timer B begins counting as soon as it is enabled.
0x1 = If Timer B is enabled (TBEN is set in the GPTMCTL register), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see. This function is valid for one-shot, periodic, and PWM modes.
|
| 5 |
TBMIE |
R/W |
0x0 |
GPTM Timer B Match Interrupt Enable.
0x0 = The match interrupt is disabled for match events. Additionally, triggers to the DMA and ADC on match events are prevented.
0x1 = An interrupt is generated when the match value in the GPTMTBMATCHR register is reached in the one-shot and periodic modes.Clearing the TBMIE bit in the GPTMTBMR register prevents assertion of µDMA or ADC requests generated on a match event. Even if the TBTODMAEN bit is set in the GPTMDMAEV register or the TBTOADCEN bit is set in the GPTMADCEV register, a µDMA or ADC match trigger is not sent to the µDMA or ADC, respectively, when the TBMIE bit is clear.
|
| 4 |
TBCDIR |
R/W |
0x0 |
GPTM Timer B Count Direction.
When in PWM or RTC mode, the status of this bit is ignored.
PWM mode always counts down and RTC mode always counts up.
0x0 = The timer counts down.
0x1 = The timer counts up. When counting up, the timer starts from a value of 0x0.
|
| 3 |
TBAMS |
R/W |
0x0 |
GPTM Timer B Alternate Mode Select.
0x0 = Capture or compare mode is enabled.
0x1 = PWM mode is enabled.To enable PWM mode, you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2.
|
| 2 |
TBCMR |
R/W |
0x0 |
GPTM Timer B Capture Mode
0x0 = Edge-Count mode
0x1 = Edge-Time mode
|
| 1-0 |
TBMR |
R/W |
0x0 |
GPTM Timer B Mode.
The timer mode is based on the timer configuration defined by bits
2:0 in the GPTMCFG register.
0x0 = Reserved
0x1 = One-Shot Timer mode
0x2 = Periodic Timer mode
0x3 = Capture mode
|