SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The AES module can assert a µDMA request for context in, context out, input data, or output data read. The AES uDMA Interrupt Mask (AES_DMAIM) register can be set to generate interrupts during the following events:
The AES module can be programmed to assert an interrupt when the uDMA has completed its last transfer. See Section 9.6 for more information.
If context and data transfers are to be handled through software, then the AES Interrupt Enable (AES_IRQENABLE), offset 0x090, can be used to enable interrupt triggering when context out, context in, data in or data out is ready. The AES Interrupt Status (AES_IRQSTATUS), offset 0x08C, indicates when an interrupt is triggered.
| Event | Description |
|---|---|
| AES_IRQSTATUS [3]: CONTEXT_OUT | Context output interrupt |
| AES_IRQSTATUS [2]: DATA_OUT | Data output interrupt |
| AES_IRQSTATUS [1]: DATA_IN | Data input interrupt |
| AES_IRQSTATUS [0]: CONTEXT_IN | Context input interrupt |