19.5.25 I2CFIFOSTATUS Register (Offset = 0xF08) [reset = 0x00010005]
I2C FIFO Status (I2CFIFOSTATUS)
This register contains the real-time status of the RX and TX FIFOs.
I2CFIFOSTATUS is shown in Figure 19-42 and described in Table 19-32.
Return to Summary Table.
Figure 19-42 I2CFIFOSTATUS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
RXABVTRIG |
RXFF |
RXFE |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x1 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
TXBLWTRIG |
TXFF |
TXFE |
| R-0x0 |
R-0x1 |
R-0x0 |
R-0x1 |
|
Table 19-32 I2CFIFOSTATUS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-19 |
RESERVED |
R |
0x0 |
|
| 18 |
RXABVTRIG |
R |
0x0 |
RX FIFO Above Trigger Level.
0x0 = The number of bytes in RX FIFO is below the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register
0x1 = The number of bytes in the RX FIFO is above the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register
|
| 17 |
RXFF |
R |
0x0 |
RX FIFO Full.
0x0 = The RX FIFO is not full.
0x1 = The RX FIFO is full.
|
| 16 |
RXFE |
R |
0x1 |
RX FIFO Empty.
0x0 = The RX FIFO is not empty.
0x1 = The RX FIFO is empty.
|
| 15-3 |
RESERVED |
R |
0x0 |
|
| 2 |
TXBLWTRIG |
R |
0x1 |
TX FIFO Below Trigger Level.
0x0 = The number of bytes in TX FIFO is above the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register
0x1 = The number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register
|
| 1 |
TXFF |
R |
0x0 |
TX FIFO Full.
0x0 = The TX FIFO is not full.
0x1 = The TX FIFO is full.
|
| 0 |
TXFE |
R |
0x1 |
TX FIFO Empty.
0x0 = The TX FIFO is not empty.
0x1 = The TX FIFO is empty.
|