SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
To carry out this operation using DMA Mode 0, an USB Tx endpoint should be programmed as follows:
When the FIFO in the USB becomes available, the USB interrupts the processor with the appropriate Tx Endpoint interrupt. The processor should then program the DMA controller as follows:
The DMA controller then requests bus mastership and transfers the packet to the USB FIFO. When it has completed the transfer, it generates a DMA interrupt. The processor should then clear the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn) register.