18.4.3 Input Edge-Count Mode
A timer is configured to Input Edge-Count mode by the following sequence:
- Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
- Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
- In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3.
- Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register.
- Program registers according to count direction:
- In down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted.
- In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. When executing an up-count, the value of the GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
- If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
- Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
- Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register.
When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4 to 8.