SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The processor implements a version of the Thumb instruction set. Table 1-23 lists the supported instructions.
NOTE
The following conventions apply in Table 1-23:
For more information on the instructions and operands, see the instruction descriptions in the Arm Cortex-M4 Technical Reference Manual.
| Mnemonic | Operands | Brief Description | Flags |
|---|---|---|---|
| ADC, ADCS | {Rd,} Rn, Op2 | Add with carry | N,Z,C,V |
| ADD, ADDS | {Rd,} Rn, Op2 | Add | N,Z,C,V |
| ADD, ADDW | {Rd,} Rn, #imm12 | Add | – |
| ADR | Rd, label | Load PC-relative address | – |
| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C |
| ASR, ASRS | Rd, Rm, <Rs|#n> | Arithmetic shift right | N,Z,C |
| B | label | Branch | – |
| BFC | Rd, #lsb, #width | Bit field clear | – |
| BFI | Rd, Rn, #lsb, #width | Bit field insert | – |
| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C |
| BKPT | #imm | Breakpoint | – |
| BL | label | Branch with link | – |
| BLX | Rm | Branch indirect with link | – |
| BX | Rm | Branch indirect | – |
| CBNZ | Rn, label | Compare and branch if nonzero | – |
| CBZ | Rn, label | Compare and branch if zero | – |
| CLREX | – | Clear exclusive | – |
| CLZ | Rd, Rm | Count leading zeros | – |
| CMN | Rn, Op2 | Compare negative | N,Z,C,V |
| CMP | Rn, Op2 | Compare | N,Z,C,V |
| CPSID | i | Change processor state, disable interrupts | – |
| CPSIE | i | Change processor state, enable interrupts | – |
| DMB | – | Data memory barrier | – |
| DSB | – | Data synchronization barrier | – |
| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C |
| ISB | – | Instruction synchronization barrier | – |
| IT | – | If-Then condition block | – |
| LDM | Rn{!}, reglist | Load multiple registers, increment after | – |
| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | – |
| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | – |
| LDR | Rt, [Rn, #offset] | Load register with word | – |
| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | – |
| LDRD | Rt, Rt2, [Rn, #offset] | Load register with 2 bytes | – |
| LDREX | Rt, [Rn, #offset] | Load register exclusive | – |
| LDREXB | Rt, [Rn] | Load register exclusive with byte | – |
| LDREXH | Rt, [Rn] | Load register exclusive with halfword | – |
| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | – |
| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | – |
| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | – |
| LDRT | Rt, [Rn, #offset] | Load register with word | – |
| LSL, LSLS | Rd, Rm, <Rs|#n> | Logical shift left | N,Z,C |
| LSR, LSRS | Rd, Rm, <Rs|#n> | Logical shift right | N,Z,C |
| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | – |
| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | – |
| MOV, MOVS | Rd, Op2 | Move | N,Z,C |
| MOV, MOVW | Rd, #imm16 | Move 16-bit constant | N,Z,C |
| MOVT | Rd, #imm16 | Move top | – |
| MRS | Rd, spec_reg | Move from special register to general register | – |
| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V |
| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z |
| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C |
| NOP | – | No operation | – |
| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C |
| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C |
| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack halfword | – |
| POP | reglist | Pop registers from stack | – |
| PUSH | reglist | Push registers onto stack | – |
| QADD | {Rd,} Rn, Rm | Saturating add | Q |
| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | – |
| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | – |
| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | – |
| QDADD | {Rd,} Rn, Rm | Saturating double and add | Q |
| QDSUB | {Rd,} Rn, Rm | Saturating double and subtract | Q |
| QSAX | {Rd,} Rn, Rm | Saturating subtract and add with exchange | – |
| QSUB | {Rd,} Rn, Rm | Saturating subtract | Q |
| QSUB16 | {Rd,} Rn, Rm | Saturating subtract 16 | – |
| QSUB8 | {Rd,} Rn, Rm | Saturating subtract 8 | – |
| RBIT | Rd, Rn | Reverse bits | – |
| REV | Rd, Rn | Reverse byte order in a word | – |
| REV16 | Rd, Rn | Reverse byte order in each halfword | – |
| REVSH | Rd, Rn | Reverse byte order in bottom halfword and sign extend | – |
| ROR, RORS | Rd, Rm, <Rs|#n> | Rotate right | N,Z,C |
| RRX, RRXS | Rd, Rm | Rotate right with extend | N,Z,C |
| RSB, RSBS | {Rd,} Rn, Op2 | Reverse subtract | N,Z,C,V |
| SADD16 | {Rd,} Rn, Rm | Signed add 16 | GE |
| SADD8 | {Rd,} Rn, Rm | Signed add 8 | GE |
| SASX | {Rd,} Rn, Rm | Signed add and subtract with exchange | GE |
| SBC, SBCS | {Rd,} Rn, Op2 | Subtract with carry | N,Z,C,V |
| SBFX | Rd, Rn, #lsb, #width | Signed bit field extract | – |
| SDIV | {Rd,} Rn, Rm | Signed divide | – |
| SEL | {Rd,} Rn, Rm | Select bytes | – |
| SEV | – | Send event | – |
| SHADD16 | {Rd,} Rn, Rm | Signed halving add 16 | – |
| SHADD8 | {Rd,} Rn, Rm | Signed halving add 8 | – |
| SHASX | {Rd,} Rn, Rm | Signed halving add and subtract with exchange | – |
| SHSAX | {Rd,} Rn, Rm | Signed halving add and subtract with exchange | – |
| SHSUB16 | {Rd,} Rn, Rm | Signed halving subtract 16 | – |
| SHSUB8 | {Rd,} Rn, Rm | Signed halving subtract 8 | – |
| SMLABB, SMLABT, SMLATB, SMLATT | Rd, Rn, Rm, Ra | Signed multiply accumulate long (halfwords) | Q |
| SMLAD, SMLADX | Rd, Rn, Rm, Ra | Signed multiply accumulate dual | Q |
| SMLAL | RdLo, RdHi, Rn, Rm | Signed multiply with accumulate (32×32+64), 64-bit result | – |
| SMLALBB, SMLALBT, SMLALTB, SMLALTT | RdLo, RdHi, Rn, Rm | Signed multiply accumulate long (halfwords) | – |
| SMLALD, SMLALDX | RdLo, RdHi, Rn, Rm | Signed multiply accumulate long dual | – |
| SMLAWB, SMLAWT | Rd, Rn, Rm, Ra | Signed multiply accumulate, word by halfword | Q |
| SMLSD SMLSDX | Rd, Rn, Rm, Ra | Signed multiply subtract dual | Q |
| SMLSLD SMLSLDX | RdLo, RdHi, Rn, Rm | Signed multiply subtract long dual | |
| SMMLA | Rd, Rn, Rm, Ra | Signed most significant word multiply accumulate | – |
| SMMLS, SMMLR | Rd, Rn, Rm, Ra | Signed most significant word multiply subtract | – |
| SMMUL, SMMULR | {Rd,} Rn, Rm | Signed most significant word multiply | – |
| SMUAD SMUADX | {Rd,} Rn, Rm | Signed dual multiply add | Q |
| SMULBB, SMULBT, SMULTB, SMULTT | {Rd,} Rn, Rm | Signed multiply halfwords | – |
| SMULL | RdLo, RdHi, Rn, Rm | Signed multiply (32×32), 64-bit result | – |
| SMULWB, SMULWT | {Rd,} Rn, Rm | Signed multiply by halfword | – |
| SMUSD, SMUSDX | {Rd,} Rn, Rm | Signed dual multiply subtract | – |
| SSAT | Rd, #n, Rm {,shift #s} | Signed saturate | Q |
| SSAT16 | Rd, #n, Rm | Signed saturate 16 | Q |
| SSAX | {Rd,} Rn, Rm | Saturating subtract and add with exchange | GE |
| SSUB16 | {Rd,} Rn, Rm | Signed subtract 16 | – |
| SSUB8 | {Rd,} Rn, Rm | Signed subtract 8 | – |
| STM | Rn{!}, reglist | Store multiple registers, increment after | – |
| STMDB, STMEA | Rn{!}, reglist | Store multiple registers, decrement before | – |
| STMFD, STMIA | Rn{!}, reglist | Store multiple registers, increment after | – |
| STR | Rt, [Rn {, #offset}] | Store register word | – |
| STRB, STRBT | Rt, [Rn {, #offset}] | Store register byte | – |
| STRD | Rt, Rt2, [Rn {, #offset}] | Store register two words | – |
| STREX | Rt, Rt, [Rn {, #offset}] | Store register exclusive | – |
| STREXB | Rd, Rt, [Rn] | Store register exclusive byte | – |
| STREXH | Rd, Rt, [Rn] | Store register exclusive halfword | – |
| STRH, STRHT | Rt, [Rn {, #offset}] | Store register halfword | – |
| STRSB, STRSBT | Rt, [Rn {, #offset}] | Store register signed byte | – |
| STRSH, STRSHT | Rt, [Rn {, #offset}] | Store register signed halfword | – |
| STRT | Rt, [Rn {, #offset}] | Store register word | – |
| SUB, SUBS | {Rd,} Rn, Op2 | Subtract | N,Z,C,V |
| SUB, SUBW | {Rd,} Rn, #imm12 | Subtract 12-bit constant | N,Z,C,V |
| SVC | #imm | Supervisor call | – |
| SXTAB | {Rd,} Rn, Rm, {,ROR #} | Extend 8 bits to 32 and add | – |
| SXTAB16 | {Rd,} Rn, Rm,{,ROR #} | Dual extend 8 bits to 16 and add | – |
| SXTAH | {Rd,} Rn, Rm,{,ROR #} | Extend 16 bits to 32 and add | – |
| SXTB16 | {Rd,} Rm {,ROR #n} | Signed extend byte 16 | – |
| SXTB | {Rd,} Rm {,ROR #n} | Sign extend a byte | – |
| SXTH | {Rd,} Rm {,ROR #n} | Sign extend a halfword | – |
| TBB | [Rn, Rm] | Table branch byte | – |
| TBH | [Rn, Rm, LSL #1] | Table branch halfword | – |
| TEQ | Rn, Op2 | Test equivalence | N,Z,C |
| TST | Rn, Op2 | Test | N,Z,C |
| UADD16 | {Rd,} Rn, Rm | Unsigned add 16 | GE |
| UADD8 | {Rd,} Rn, Rm | Unsigned add 8 | GE |
| UASX | {Rd,} Rn, Rm | Unsigned add and subtract with exchange | GE |
| UHADD16 | {Rd,} Rn, Rm | Unsigned halving add 16 | – |
| UHADD8 | {Rd,} Rn, Rm | Unsigned halving add 8 | – |
| UHASX | {Rd,} Rn, Rm | Unsigned halving add and subtract with exchange | – |
| UHSAX | {Rd,} Rn, Rm | Unsigned halving subtract and add with exchange | – |
| UHSUB16 | {Rd,} Rn, Rm | Unsigned halving subtract 16 | – |
| UHSUB8 | {Rd,} Rn, Rm | Unsigned halving subtract 8 | – |
| UBFX | Rd, Rn, #lsb, #width | Unsigned bit field extract | – |
| UDIV | {Rd,} Rn, Rm | Unsigned divide | – |
| UMAAL | RdLo, RdHi, Rn, Rm | Unsigned multiply accumulate accumulate long (32×32+64), 64-bit result | – |
| UMLAL | RdLo, RdHi, Rn, Rm | Unsigned multiply with accumulate (32×32+32+32), 64-bit result | – |
| UMULL | RdLo, RdHi, Rn, Rm | Unsigned multiply (32×32), 64-bit result | – |
| UQADD16 | {Rd,} Rn, Rm | Unsigned saturating add 16 | – |
| UQADD8 | {Rd,} Rn, Rm | Unsigned saturating add 8 | – |
| UQASX | {Rd,} Rn, Rm | Unsigned saturating add and subtract with exchange | – |
| UQSAX | {Rd,} Rn, Rm | Unsigned saturating subtract and add with exchange | – |
| UQSUB16 | {Rd,} Rn, Rm | Unsigned saturating subtract 16 | – |
| UQSUB8 | {Rd,} Rn, Rm | Unsigned saturating subtract 8 | – |
| USAD8 | {Rd,} Rn, Rm | Unsigned sum of absolute differences | – |
| USADA8 | {Rd,} Rn, Rm, Ra | Unsigned sum of absolute differences and accumulate | – |
| USAT | Rd, #n, Rm {,shift #s} | Unsigned saturate | Q |
| USAT16 | Rd, #n, Rm | Unsigned saturate 16 | Q |
| USAX | {Rd,} Rn, Rm | Unsigned subtract and add with exchange | GE |
| USUB16 | {Rd,} Rn, Rm | Unsigned subtract 16 | GE |
| USUB8 | {Rd,} Rn, Rm | Unsigned subtract 8 | GE |
| UXTAB | {Rd,} Rn, Rm, {,ROR #} | Rotate, extend 8 bits to 32 and add | – |
| UXTAB16 | {Rd,} Rn, Rm, {,ROR #} | Rotate, dual extend 8 bits to 16 and add | – |
| UXTAH | {Rd,} Rn, Rm, {,ROR #} | Rotate, unsigned extend and add halfword | – |
| UXTB | {Rd,} Rm, {,ROR #n} | Zero extend a Byte | – |
| UXTB16 | {Rd,} Rm, {,ROR #n} | Unsigned extend byte 16 | – |
| UXTH | {Rd,} Rm, {,ROR #n} | Zero extend a halfword | – |
| VABS.F32 | Sd, Sm | Floating-point absolute | – |
| VADD.F32 | {Sd,} Sn, Sm | Floating-point add | – |
| VCMP.F32 | Sd, <Sm | #0.0> | Compare two floating-point registers, or one floating-point register and zero | FPSCR |
| VCMPE.F32 | Sd, <Sm | #0.0> | Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check | FPSCR |
| VCVT.S32.F32 | Sd, Sm | Convert between floating-point and integer | – |
| VCVT.S16.F32 | Sd, Sd, #fbits | Convert between floating-point and fixed point | – |
| VCVTR.S32.F32 | Sd, Sm | Convert between floating-point and integer with rounding | – |
| VCVT<B|H>.F32.F16 | Sd, Sm | Converts half-precision value to single-precision | – |
| VCVTT<B|T>.F32.F16 | Sd, Sm | Converts single-precision register to half-precision | – |
| VDIV.F32 | {Sd,} Sn, Sm | Floating-point divide | – |
| VFMA.F32 | {Sd,} Sn, Sm | Floating-point fused multiply accumulate | – |
| VFNMA.F32 | {Sd,} Sn, Sm | Floating-point fused negate multiply accumulate | – |
| VFMS.F32 | {Sd,} Sn, Sm | Floating-point fused multiply subtract | – |
| VFNMS.F32 | {Sd,} Sn, Sm | Floating-point fused negate multiply subtract | – |
| VLDM.F<32|64> | Rn{!}, list | Load multiple extension registers | – |
| VLDR.F<32|64> | <Dd|Sd>, [Rn] | Load an extension register from memory | – |
| VLMA.F32 | {Sd,} Sn, Sm | Floating-point multiply accumulate | – |
| VLMS.F32 | {Sd,} Sn, Sm | Floating-point multiply subtract | – |
| VMOV.F32 | Sd, #imm | Floating-point move immediate | – |
| VMOV | Sd, Sm | Floating-point move register | – |
| VMOV | Sn, Rt | Copy Arm core register to single precision | – |
| VMOV | Sm, Sm1, Rt, Rt2 | Copy two Arm core registers to two single precision | – |
| VMOV | Dd[x], Rt | Copy Arm core register to scalar | – |
| VMOV | Rt, Dn[x] | Copy scalar to Arm core register | – |
| VMRS | Rt, FPSCR | Move FPSCR to Arm core register or APSR | N,Z,C,V |
| VMSR | FPSCR, Rt | Move to FPSCR from Arm Core register | FPSCR |
| VMUL.F32 | {Sd,} Sn, Sm | Floating-point multiply | – |
| VNEG.F32 | Sd, Sm | Floating-point negate | – |
| VNMLA.F32 | {Sd,} Sn, Sm | Floating-point multiply and add | – |
| VNMLS.F32 | {Sd,} Sn, Sm | Floating-point multiply and subtract | – |
| VNMUL | {Sd,} Sn, Sm | Floating-point multiply | – |
| VPOP | list | Pop extension registers | – |
| VPUSH | list | Push extension registers | – |
| VSQRT.F32 | Sd, Sm | Calculates floating-point square root | – |
| VSTM | Rn{!}, list | Floating-point register store multiple | – |
| VSTR.F3<32|64> | Sd, [Rn] | Stores an extension register to memory | – |
| VSUB.F<32|64> | {Sd,} Sn, Sm | Floating-point subtract | – |
| WFE | – | Wait for event | – |
| WFI | – | Wait for interrupt | – |