SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The flash memory controller can generate interrupts when the following conditions are observed:
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see Section 7.3.5) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible through the Flash Controller Raw Interrupt Status (FCRIS) register (see Section 7.3.4).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see Section 7.3.6).