SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
NOTE
While the device is connected through JTAG, the LDO control settings for sleep and deep-sleep modes are not available and cannot be applied.
Software can configure the LDOSPCTL register (see Section 4.2.25) or the LDODPCTL register (see Section 4.2.27) to dynamically raise or lower the LDO voltage in sleep or deep-sleep mode, depending on whether an increase in performance or reduction in power consumption is required. The VLDO field in the LDOSPCTL register is set to 1.2 V by default. The LDODPCTL register is set to an LDO voltage of 0.9 V by default. If an application requires performance over power consumption in deep-sleep mode, the deep-sleep LDO voltage can be configured to a voltage greater than 0.9 V during system control initialization by setting the VADJEN bit and programming the VLDO field of the LDODPCTL register.
Before the LDO level is lowered during sleep or deep-sleep mode, the system clock must be configured to an acceptable frequency in the RSCLKCFG register for sleep mode and in DSLPCLKCFG for deep-sleep mode. Table 4-8 lists the maximum system clock and PIOSC frequencies with respect to the LDO voltage.
| Operating Voltage (LDO) | Maximum System Clock Frequency | PIOSC |
|---|---|---|
| 1.2 V | 120 MHz | 16 MHz |
| 0.9 V | 30 MHz | 16 MHz |
The LDO power calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for the LDO in the various modes. If software requests an LDO value that is too low or too high, the value is not accepted and an error is reported in the SDPMST register.
NOTE
When using the USB, Ethernet, EPI, and QSSI interfaces, the LDO must be configured to 1.2 V.