SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The integrated LIDD controller has programmable timing parameters that support a wide variety of character-based LCD panels. Alternatively, the DMA module can mimic the CPU and perform a sequence of write-only data bus transactions to the character-based LCD panel.
LIDD mode is enabled by clearing the LCDMODE bit in the LCD Control (LCDCTL) register.
LIDD Controller operation is summarized as follows:
Table 20-1 describes how the signals are used to interface to external LCD modules, which are configured by the LCDLIDDCTL register.
Display Type | Interface Type | Data Bits | LCDLIDDCTL [2:0] | Signal Name | LCD Display I/O Name | LCD Display I/O Description |
---|---|---|---|---|---|---|
Character Display | HD44780 Type | 4 | 0x4 | LCDDATA[7:4] | DATA[7:4] | LCD data bus (length defined by instruction) |
LCDAC | E (or E0) | Enable strobe (first display) | ||||
LCDLP | R/W | Read/Write | ||||
LCDFP | RS | Register select (data/not instruction) | ||||
LCDMCLK | E1 | Enable strobe (second display optional) | ||||
Character Display | HD44780 Type | 8 | 0x4 | LCDDATA[7:0] | DATA[7:0] | LCD data bus (length defined by instruction) |
LCDAC | E (or E0) | Enable strobe (first display) | ||||
LCDLP | R/W | Read/Write | ||||
LCDFP | RS | Register select (data/not instruction | ||||
LCDMCLK | E1 | Enable strobe (second display optional) | ||||
Micro Interface Graphic Display | 6800 Family | Up to 16 | 0x1 | LCDDATA[15:0] | DATA[15:0] | LCD data bus (16 bits always available) |
LCDCP | E | Enable clock | ||||
LCDLP | R/W | Read/Write | ||||
LCDFP | A0 | Address and data select | ||||
LCDAC | CS (or CS0) | Chip select (first display) | ||||
LCDMCLK | CS1 | Chip select (second display optional) | ||||
0x0 | LCDMCLK | None | Synchronous clock (optional) | |||
Micro Interface Graphic Display | 8080 Family | Up to 16 | 0x3 | LCDDATA[15:0] | DATA[15:0] | LCD data bus (16 bits always available) |
LCDCP | RD | Read strobe | ||||
LCDLP | WR | Write strobe | ||||
LCDFP | A0 | Address and data select | ||||
LCDAC | CS (or CS0) | Chip select (first display) | ||||
LCDMCLK | CS1 | Chip select (second display optional) | ||||
0x2 | LCDMCLK | None | Synchronous clock (optional) |