15.3.1.2 Media-Independent Interface (MII)
Four clock inputs are driven into the Ethernet MAC when the MII configuration is enabled. The clocks are described as follows:
- Gated system clock (SYSCLK): The SYSCLK signal acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep, and Deep Sleep mode is programmed in the System Control module. See Section 4 for more information on programming SYSCLK and enabling the Ethernet MAC.
- MOSC: A gated version of the MOSC clock is provided as the PTP reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a maximum frequency of 25 MHz. See Section 15.3.6 for more information.
- EN0RXCK: This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz, depending on whether the device is operating at 10 Mbps or 100 Mbps.
- EN0TXCK: This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz, depending on whether the device is operating at 10 Mbps or 100 Mbps.
Figure 15-3 shows the clock inputs for an MII.