SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pullup and pulldown resistors, slew-rate control and digital input enable for each GPIO. If 3.3 V is applied to a GPIO configured as an open-drain output, the output voltage will depend on the strength of your pullup resistor. The GPIO pad is not electrically configured to output 3.3 V.
NOTE
Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR .
NOTE
Port pins PM[7:4] operate as Fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. 10- and 12-mA drive are not supported. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins.