4.1.5.2.1.3.1 PHY Interface Clocking
The Ethernet Controller module and Integrated PHY receive two clock inputs (see Section 15.3.1.1 for more information):
- A gated system clock acts as the clock source to the CSRs of the Ethernet MAC. The SysClk frequency for run, sleep, and deep-sleep modes is programmed in the System Control module.
- The PHY receives the MOSC, which must be 25 MHz ±50 ppm for proper operation. The MOSC source can be a single-ended source or a crystal.