SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The user is provided execution protection through 16 pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers.
The policies can be combined as listed in Table 7-2.
| FMPPEn | FMPREn | Protection |
|---|---|---|
| 0 | 0 | Execute-only protection. The block can only be executed and cannot be written or erased. This mode is used to protect code. |
| 1 | 0 | The block can be written, erased, or executed, but cannnot be read. This combination is unlikely to be used. |
| 0 | 1 | Read-only protection. The block can be read or executed but cannot be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. |
| 1 | 1 | No protection. The block can be written, erased, executed, or read. |
A flash memory access that attempts to read a read-protected block (FMPREn bit is clear) is prohibited and generates a bus fault. A flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is clear) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits can be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from 1 to 0 and not committed, it can be restored by executing a simulated power-on-reset (SIM_POR) event. The changes are committed using the Flash Memory Control (FMC) register. For details on programming these bits, see Section 7.2.3.12.