21.5.1 PWMCTL Register (Offset = 0x0) [reset = 0x0]
PWM Master Control (PWMCTL)
This register provides master control over the PWM generation blocks.
PWMCTL is shown in Figure 21-7 and described in Table 21-3.
Return to Summary Table.
Figure 21-7 PWMCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
GLOBALSYNC3 |
GLOBALSYNC2 |
GLOBALSYNC1 |
GLOBALSYNC0 |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 21-3 PWMCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
GLOBALSYNC3 |
R/W |
0x0 |
Update PWM Generator 3. This bit automatically clears when the updates have completed; it cannot be cleared by software.
0x0 = No effect.
0x1 = Any queued update to a load or comparator register in PWM generator 3 is applied the next time the corresponding counter becomes zero.
|
| 2 |
GLOBALSYNC2 |
R/W |
0x0 |
Update PWM Generator 2. This bit automatically clears when the updates have completed; it cannot be cleared by software.
0x0 = No effect.
0x1 = Any queued update to a load or comparator register in PWM generator 2 is applied the next time the corresponding counter becomes zero.
|
| 1 |
GLOBALSYNC1 |
R/W |
0x0 |
Update PWM Generator 1. This bit automatically clears when the updates have completed; it cannot be cleared by software.
0x0 = No effect.
0x1 = Any queued update to a load or comparator register in PWM generator 1 is applied the next time the corresponding counter becomes zero.
|
| 0 |
GLOBALSYNC0 |
R/W |
0x0 |
Update PWM Generator 0. This bit automatically clears when the updates have completed; it cannot be cleared by software.
0x0 = No effect.
0x1 = Any queued update to a load or comparator register in PWM generator 0 is applied the next time the corresponding counter becomes zero.
|