21.5.15 PWMnISC Register [reset = 0x0]
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C
These registers provide the current set of interrupt sources that are asserted to the interrupt controller (PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not enabled. These are RW1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.
NOTE
The interrupt status can only be cleared one PWM Clock cycle after the interrupt occurs. The larger the PWM Clock Divider (PWMDIV) value in PWMCC register, the longer the system delay is to clear the interrupt.
PWMnISC is shown in Figure 21-21 and described in Table 21-17.
Return to Summary Table.
Figure 21-21 PWMnISC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTCMPBD |
INTCMPBU |
INTCMPAD |
INTCMPAU |
INTCNTLOAD |
INTCNTZERO |
| R-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
|
Table 21-17 PWMnISC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-6 |
RESERVED |
R |
0x0 |
|
| 5 |
INTCMPBD |
R/W1C |
0x0 |
Comparator B down interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPBD bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCMPBD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 4 |
INTCMPBU |
R/W1C |
0x0 |
Comparator B up interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPBU bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCMPBU bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 3 |
INTCMPAD |
R/W1C |
0x0 |
Comparator A down interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPAD bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 2 |
INTCMPAU |
R/W1C |
0x0 |
Comparator A up interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPAU bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCMPAU bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 1 |
INTCNTLOAD |
R/W1C |
0x0 |
Counter=Load interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCNTLOAD bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 0 |
INTCNTZERO |
R/W1C |
0x0 |
Counter=0 interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTCNTZERO bit in the PWMnRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTCNTZERO bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller.
|