SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Load (PWM0LOAD), offset 0x050
PWM1 Load (PWM1LOAD), offset 0x090
PWM2 Load (PWM2LOAD), offset 0x0D0
PWM3 Load (PWM3LOAD), offset 0x110
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on). Based on the counter mode configured by the MODE bit in the PWMnCTL register, this value is either loaded into the counter after it reaches zero or is the limit of up-counting after which the counter decrements back to zero. When this value matches the counter, a pulse is output which can be configured to drive the generation of the pwmA and/or pwmB signal (via the PWMnGENA / PWMnGENB register) or drive an interrupt or ADC trigger (via the PWMnINTEN register).
If the Load Value Update mode is locally synchronized (based on the LOADUPD field encoding in the PWMnCTL register), the 16-bit LOAD value is used the next time the counter reaches zero. If the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see Section 21.5.1). If this register is re-written before the actual update occurs, the previous value is never used and is lost.
PWMnLOAD is shown in Figure 21-22 and described in Table 21-18.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LOAD | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||