24.5.10 QEIRIS Register (Offset = 0x24) [reset = 0x0]
QEI Raw Interrupt Status (QEIRIS)
This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register). If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEIRIS is shown in Figure 24-13 and described in Table 24-12.
Return to Summary Table.
Figure 24-13 QEIRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTERROR |
INTDIR |
INTTIMER |
INTINDEX |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 24-12 QEIRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
INTERROR |
R |
0x0 |
Phase Error Detected. The INTERROR bit is only applicable when the QEI is operating in quadrature phase mode (SIGMODE =0). This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC register.
0x0 = An interrupt has not occurred.
0x1 = A phase error has been detected.
|
| 2 |
INTDIR |
R |
0x0 |
Direction Change Detected. This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register.
0x0 = An interrupt has not occurred.
0x1 = The rotation direction has changed
|
| 1 |
INTTIMER |
R |
0x0 |
Velocity Timer Expired. This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC register.
0x0 = An interrupt has not occurred.
0x1 = The velocity timer has expired.
|
| 0 |
INTINDEX |
R |
0x0 |
Index Pulse Asserted. This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC register.
0x0 = An interrupt has not occurred.
0x1 = The index pulse has occurred.
|