SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The MAC captures the timestamp of all received frames. The MAC does not process the received frames to identify the PTP frames in default timestamping mode (when Advanced Timestamp is disabled). The MAC gives the timestamp and the corresponding status to the TX/RX Controller along with the EOF data. The TX/RX Controller validates and indicates the availability of the timestamp so that the DMA can return the timestamp to the corresponding receive descriptor. The 64-bit timestamp information is written to the RDES6 and RDES7 fields. The timestamp is written only to the receive descriptor for which the Last Descriptor status field has been set to 1 (the EOF marker). When the timestamp is not available (for example, because of an RX FIFO overflow), an all '1s' pattern is written to the descriptors (RDES6 and RDES7), indicating that the timestamp is not correct. If timestamping is disabled, the DMA does not alter RDES6 or RDES7. RDES0[7] indicates whether the timestamp is updated in RDES6 and RDES7.