SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Ethernet MAC has the ability to read or write to the PHY registers through the EN0MDIO and EN0MDC signals of the Serial Management Interface defined by the IEEE 802.3 standard. The internal EN0MDIO and EN0MDC signals connect to the integrated PHY as well as to the external EN0MDIO and EN0MDC pins. The EN0MDC signal is a 2.5-MHz clock that is sourced from System Clock (SYSCLK) and then divided down to the required frequency by programming the CR field in the Ethernet MAC MII Address (EMACMIIADDR) register. To access the integrated PHY, the PLA field in the EMACMIIADDR register must be 0x0. The available addresses for external PHYs are 0x01 to 0x1F.