23.5.4 SSISR Register (Offset = 0xC) [reset = 0x3]
QSSI Status (SSISR), offset 0x00C
The SSISR register contains bits that indicate the FIFO fill status and the QSSI busy status.
SSISR is shown in Figure 23-13 and described in Table 23-9.
Return to Summary Table.
Figure 23-13 SSISR Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
BSY |
RFF |
RNE |
TNF |
TFE |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x1 |
R-0x1 |
|
Table 23-9 SSISR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
BSY |
R |
0x0 |
QSSI Busy Bit
0x0 = The QSSI is idle.
0x1 = The QSSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty.
|
| 3 |
RFF |
R |
0x0 |
QSSI Receive FIFO Full
0x0 = The receive FIFO is not full.
0x1 = The receive FIFO is full.
|
| 2 |
RNE |
R |
0x0 |
QSSI Receive FIFO Not Empty
0x0 = The receive FIFO is empty.
0x1 = The receive FIFO is not empty.
|
| 1 |
TNF |
R |
0x1 |
QSSI Transmit FIFO Not Full
0x0 = The transmit FIFO is full.
0x1 = The transmit FIFO is not full.
|
| 0 |
TFE |
R |
0x1 |
QSSI Transmit FIFO Empty
0x0 = The transmit FIFO is not empty.
0x1 = The transmit FIFO is empty.
|