5.2.1 SYSEXCRIS Register (Offset = 0x0) [reset = 0x0]
System Exception Raw Interrupt Status (SYSEXCRIS)
The SYSEXCRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect.
SYSEXCRIS is shown in Figure 5-1 and described in Table 5-3.
Return to Summary Table.
Figure 5-1 SYSEXCRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
FPIXCRIS |
FPOFCRIS |
FPUFCRIS |
FPIOCRIS |
FPDZCRIS |
FPIDCRIS |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 5-3 SYSEXCRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-6 |
RESERVED |
R |
0x0 |
|
| 5 |
FPIXCRIS |
R |
0x0 |
Floating-Point Inexact Exception Raw Interrupt Status
This bit is cleared by writing 1 to the IXCIC bit in the SYSEXCIC register.
|
| 4 |
FPOFCRIS |
R |
0x0 |
Floating-Point Overflow Exception Raw Interrupt Status
This bit is cleared by writing 1 to the OFCIC bit in the SYSEXCIC register.
|
| 3 |
FPUFCRIS |
R |
0x0 |
Floating-Point Underflow Exception Raw Interrupt Status
This bit is cleared by writing 1 to the UFCIC bit in the SYSEXCIC register.
|
| 2 |
FPIOCRIS |
R |
0x0 |
Floating-Point Invalid Operation Raw Interrupt Status
This bit is cleared by writing 1 to the IOCIC bit in the SYSEXCIC register.
|
| 1 |
FPDZCRIS |
R |
0x0 |
Floating-Point Divide By 0 Exception Raw Interrupt Status
This bit is cleared by writing 1 to the DZCIC bit in the SYSEXCIC register.
|
| 0 |
FPIDCRIS |
R |
0x0 |
Floating-Point Input Denormal Exception Raw Interrupt Status
This bit is cleared by writing 1 to the IDCIC bit in the SYSEXCIC register.
|