2.5.11 SYSHNDCTRL Register (Offset = 0xD24) [reset = 0x0]
System Handler Control and State (SYSHNDCTRL)
NOTE
This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type.
NOTE
Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified.
SYSHNDCTRL is shown in Figure 2-23 and described in Table 2-36.
Return to Summary Table.
Figure 2-23 SYSHNDCTRL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
USAGE |
BUS |
MEM |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| SVC |
BUSP |
MEMP |
USAGEP |
TICK |
PNDSV |
RESERVED |
MON |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| SVCA |
RESERVED |
USGA |
RESERVED |
BUSA |
MEMA |
| R/W-0x0 |
R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 2-36 SYSHNDCTRL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-19 |
RESERVED |
R |
0x0 |
|
| 18 |
USAGE |
R/W |
0x0 |
Usage Fault Enable
|
| 17 |
BUS |
R/W |
0x0 |
Bus Fault Enable
|
| 16 |
MEM |
R/W |
0x0 |
Memory Management Fault Enable
|
| 15 |
SVC |
R/W |
0x0 |
SVC Call Pending
This bit can be modified to change the pending status of the SVC call exception.
|
| 14 |
BUSP |
R/W |
0x0 |
Bus Fault Pending
This bit can be modified to change the pending status of the bus fault exception.
|
| 13 |
MEMP |
R/W |
0x0 |
Memory Management Fault Pending
This bit can be modified to change the pending status of the memory management fault exception.
|
| 12 |
USAGEP |
R/W |
0x0 |
Usage Fault Pending
This bit can be modified to change the pending status of the usage fault exception.
|
| 11 |
TICK |
R/W |
0x0 |
SysTick Exception Active
This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit.
|
| 10 |
PNDSV |
R/W |
0x0 |
PendSV Exception Active
This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit.
|
| 9 |
RESERVED |
R |
0x0 |
|
| 8 |
MON |
R/W |
0x0 |
Debug Monitor Active
|
| 7 |
SVCA |
R/W |
0x0 |
SVC Call Active
This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit.
|
| 6-4 |
RESERVED |
R |
0x0 |
|
| 3 |
USGA |
R/W |
0x0 |
Usage Fault Active
This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
BUSA |
R/W |
0x0 |
Bus Fault Active
This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit.
|
| 0 |
MEMA |
R/W |
0x0 |
Memory Management Fault Active
This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit.
|