SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost.
By default, the internal pullup resistor on the TCK pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pullup and pulldown resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source (see Section 17.5.15 and Section 17.5.16).