27.5.20 ULPIREGCTL Register (Offset = 0x76) [reset = 0x0]
USB ULPI Register Control (ULPIREGCTL)
OTG A / Host
OTG B / Device
The ULPIREGCTL register contains control and status bits relating to the register being read/written through the ULPI interface.
ULPIREGCTL is shown in Figure 27-25 and described in Table 27-30.
Return to Summary Table.
Figure 27-25 ULPIREGCTL Register
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
RDWR |
REGCMPLT |
REGACC |
| R-0x0 |
R/W-0x0 |
R/W0-0x0 |
R/W-0x0 |
|
Table 27-30 ULPIREGCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7-3 |
RESERVED |
R |
0x0 |
|
| 2 |
RDWR |
R/W |
0x0 |
Read/Write Control.
0x0 = Write access
0x1 = Read access
|
| 1 |
REGCMPLT |
R/W0 |
0x0 |
Register Access Complete.
This bit is set by the link when the register access is complete and must be cleared by software. |
| 0 |
REGACC |
R/W |
0x0 |
Initiate Register Access.
This bit is used to initiate a register access and is cleared automatically when the register access is complete and REGCMPLT = 1.
0x0 = Register access complete
0x1 = Initiate register access
|