SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The CPU may update the data bytes of a Transmit Message Object any time using the CAN Interface Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the CANIFnMCTL register need to be cleared before the update.
Even if only some of the data bytes are to be updated, all four bytes of the corresponding CANIFnDAn / CANIFnDBn register must be valid before the content of that register is transferred to the message object. Either the CPU must write all four bytes into the CANIFnDAn / CANIFnDBn register or the message object is transferred to the CANIFnDAn / CANIFnDBn register before the CPU writes the new data bytes.
To only update the data in a message object, the WRNRD, DATAA, and DATAB bits in the CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission that may already be in progress while the data is updated, the NEWDAT and TXRQST bits must be set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT is cleared as soon as the new transmission has started.