SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB DMA Address 0 (USBDMAADDR0), offset 0x208
USB DMA Address 1 (USBDMAADDR1), offset 0x218
USB DMA Address 2 (USBDMAADDR2), offset 0x228
USB DMA Address 3 (USBDMAADDR3), offset 0x238
USB DMA Address 4 (USBDMAADDR4), offset 0x248
USB DMA Address 5 (USBDMAADDR5), offset 0x258
USB DMA Address 6 (USBDMAADDR6), offset 0x268
USB DMA Address 7 (USBDMAADDR7), offset 0x278
OTG A / Host
OTG B / Device
This register provides the DMA transfer control for each channel. The enabling, transfer direction, transfer mode, the DMA burst modes are all controlled by this register.
USBDMAADDRn is shown in Figure 27-63 and described in Table 27-70.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DMAADDR | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMAADDR | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMAADDR | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMAADDR | RESERVED | ||||||
R/W-0x0 | R-0x0 | ||||||