SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB DMA Count 0 (USBDMACOUNT0), offset 0x20C
USB DMA Count 1 (USBDMACOUNT1), offset 0x21C
USB DMA Count 2 (USBDMACOUNT2), offset 0x22C
USB DMA Count 3 (USBDMACOUNT3), offset 0x23C
USB DMA Count 4 (USBDMACOUNT4), offset 0x24C
USB DMA Count 5 (USBDMACOUNT5), offset 0x25C
USB DMA Count 6 (USBDMACOUNT6), offset 0x26C
USB DMA Count 7 (USBDMACOUNT7), offset 0x27C
OTG A / Host
OTG B / Device
This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer which identifies the entire transfer length. As the count progresses this count is decremented as bytes are transferred.
USBDMACOUNTn is shown in Figure 27-64 and described in Table 27-71.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DMACOUNT | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMACOUNT | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACOUNT | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACOUNT | RESERVED | ||||||
R/W-0x0 | R-0x0 | ||||||