27.5.50 USBDMAINTR Register (Offset = 0x200) [reset = 0x0]
USB DMA Interrupt (USBDMAINTR)
OTG A / Host
OTG B / Device
This register provides an interrupt for each USB DMA channel. This interrupt register is cleared when read. When any bit of this register is set, an interrupt is sent to the interrupt controller. Bits in this register will only be set if the corresponding enable bit in the DMACTLn register is set.
USBDMAINTR is shown in Figure 27-61 and described in Table 27-68.
Return to Summary Table.
Figure 27-61 USBDMAINTR Register
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CH7DMAINT |
CH6DMAINT |
CH5DMAINT |
CH4DMAINT |
CH3DMAINT |
CH2DMAINT |
CH1DMAINT |
CH0DMAINT |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 27-68 USBDMAINTR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
CH7DMAINT |
R/W |
0x0 |
Channel 7 DMA Interrupt.
0x0 = No effect
0x1 = Channel 7 DMA interrupt enabled.
|
| 6 |
CH6DMAINT |
R/W |
0x0 |
Channel 6 DMA Interrupt.
0x0 = No effect
0x1 = Channel 6 DMA interrupt enabled.
|
| 5 |
CH5DMAINT |
R/W |
0x0 |
Channel 5 DMA Interrupt.
0x0 = No effect
0x1 = Channel 5 DMA interrupt enabled.
|
| 4 |
CH4DMAINT |
R/W |
0x0 |
Channel 4 DMA Interrupt.
0x0 = No effect
0x1 = Channel 4 DMA interrupt enabled.
|
| 3 |
CH3DMAINT |
R/W |
0x0 |
Channel 3 DMA Interrupt.
0x0 = No effect
0x1 = Channel 3 DMA interrupt enabled.
|
| 2 |
CH2DMAINT |
R/W |
0x0 |
Channel 2 DMA Interrupt.
0x0 = No effect
0x1 = Channel 2 DMA interrupt enabled.
|
| 1 |
CH1DMAINT |
R/W |
0x0 |
Channel 1 DMA Interrupt.
0x0 = No effect
0x1 = Channel 1 DMA interrupt enabled.
|
| 0 |
CH0DMAINT |
R |
0x0 |
Channel 0 DMA Interrupt.
0x0 = No effect
0x1 = Channel 0 DMA interrupt enabled.
|