| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
ERR |
R/W |
0x0 |
LPM Error Interrupt Mask.
0x0 = The ERR bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The ERR bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 4 |
RES |
R/W |
0x0 |
LPM Resume Interrupt Mask.
0x0 = The RES bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The RES bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 3 |
NC |
R/W |
0x0 |
LPM NC Interrupt Mask.
0x0 = The NC bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The NC bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 2 |
ACK |
R/W |
0x0 |
LPM ACK Interrupt Mask.
0x0 = The ACK bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The ACK bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 1 |
NY |
R/W |
0x0 |
LPM NY Interrupt Mask.
0x0 = The NY bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The NY bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 0 |
STALL |
R/W |
0x0 |
LPM STALL Interrupt Mask.
0x0 = The STALL bit in the USBLPMRIS registers is masked and does not cause an interrupt
0x1 = The STALL bit in the USBLPMRIS register is not masked and can trigger an interrupt to the interrupt controller.
|