SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Memory Power Control (USBMPC)
This register provides power control to the peripheral memory array.
NOTE
If the PWRCTL field of the USBMPC register is set to 0x3 and the power domain to the USB is turned off by writing 0 to the P0 bit of the PCUSB register, then the SRAM goes into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).
USBMPC is shown in Figure 4-39 and described in Table 4-46.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRCTL | ||||||||||||||
R-0x0 | R/W-0x3 | ||||||||||||||