SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138
USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148
USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158
USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168
USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178
OTG A / Host
OTG B / Device
NOTE
The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit in the USBRXCSRLn register is set.
USBRXCOUNTn is a 16-bit read-only register that holds the number of data bytes in the packet currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk packets, the number given is for the combined packet.
USBRXCOUNTn is shown in Figure 27-56 and described in Table 27-61.
Return to Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | COUNT | ||||||
| R-0x0 | R-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COUNT | |||||||
| R-0x0 | |||||||