27.5.44 USBRXCSRHn Register [reset = 0x0]
USB Receive Control and Status Endpoint n High (USBRXCSRHn) USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177
OTG A / Host
OTG B / Device
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers through the currently selected receive endpoint.
USBRXCSRHn for OTG A / Host is shown in Figure 27-54 and described in Table 27-59.
USBRXCSRHn for OTG B / Device is shown in Figure 27-55 and described in Table 27-60.
Return to Summary Table.
Figure 27-54 USBRXCSRHn Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| AUTOCL |
AUTORQ |
DMAEN |
PIDERR |
DMAMOD |
DTWE |
DT |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 27-59 USBRXCSRHn Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
AUTOCL |
R/W |
0x0 |
Auto Clear.
0x0 = No effect.
0x1 = Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using USB DMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see .
|
| 6 |
AUTORQ |
R/W |
0x0 |
Auto Request.
This bit is automatically cleared when a short packet is received.
0x0 = No effect.
0x1 = Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared.
|
| 5 |
DMAEN |
R/W |
0x0 |
DMA Request Enable.
0x0 = Disables the USB DMA request for the receive endpoint.
0x1 = Enables the USB DMA request for the receive endpoint.
|
| 4 |
PIDERR |
R/W |
0x0 |
PID Error.
This bit is ignored in bulk or interrupt transactions.
0x0 = No error.
0x1 = Indicates a PID error in the received packet of an isochronous transaction.
|
| 3 |
DMAMOD |
R/W |
0x0 |
DMA Request Mode.
This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared.
0x0 = An interrupt is generated after every USB DMA packet transfer.
0x1 = An interrupt is generated only after the entire USB DMA transfer is complete.
|
| 2 |
DTWE |
R |
0x0 |
Data Toggle Write Enable.
This bit is automatically cleared once the new value is written.
0x0 = The DT bit cannot be written.
0x1 = Enables the current state of the receive endpoint data to be written (see DT bit).
|
| 1 |
DT |
R |
0x0 |
Data Toggle.
When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the data toggle.
If DTWE is Low, any value written to this bit is ignored.
Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. |
| 0 |
RESERVED |
R |
0x0 |
|
Figure 27-55 USBRXCSRHn Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| AUTOCL |
ISO |
DMAEN |
DISNYET/PIDERR |
DMAMOD |
RESERVED |
INCOMPRX |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W0C-0x0 |
|
Table 27-60 USBRXCSRHn Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
AUTOCL |
R/W |
0x0 |
Auto Clear.
0x0 = No effect.
0x1 = Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using USB DMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see.
|
| 6 |
ISO |
R/W |
0x0 |
Isochronous Transfers.
0x0 = Enables the receive endpoint for isochronous transfers.
0x1 = Enables the receive endpoint for bulk/interrupt transfers.
|
| 5 |
DMAEN |
R/W |
0x0 |
DMA Request Enable.
0x0 = Disables the USB DMA request for the receive endpoint.
0x1 = Enables the USB DMA request for the receive endpoint.
|
| 4 |
DISNYET/PIDERR |
R/W |
0x0 |
Disable NYET / PID Error.
0x0 = No effect.
0x1 = For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all successfully received packets are acknowledged, including at the point at which the FIFO becomes full.
For isochronous transactions: Indicates a PID error in the received packet.
|
| 3 |
DMAMOD |
R/W |
0x0 |
DMA Request Mode.
This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared.
0x0 = An interrupt is generated after every USB DMA packet transfer.
0x1 = An interrupt is generated only after the entire USB DMA transfer is complete.
|
| 2-1 |
RESERVED |
R |
0x0 |
|
| 0 |
INCOMPRX |
R/W0C |
0x0 |
Incomplete RX Transmission Status.
In anything other than an Isochronous transfer, this bit returns a 0.
0x0 = No effect.
0x1 = Indicates that the packet in the RX FIFO is incomplete because parts of the data were not received in the high-bandwidth/Isochronous transfer
|