SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130
USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140
USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150
USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160
USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170
OTG A / Host
OTG B / Device
The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred through the transmit endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value to this register.
NOTE
USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in USB DMA Basic Mode.
USBTXMAXPn is shown in Figure 27-46 and described in Table 27-51.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MAXLOAD | ||||||
| R-0x0 | R/W-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAXLOAD | |||||||
| R/W-0x0 | |||||||