New TI high-speed ADCs now have LVDS outputs that are up to 18 bits. These devices are available on an EVM that connect directly to the TSW1418EVM. The common connector between the EVMs and the TSW1418EVM is a Samtec 400-pin, high-speed, high-density FMC connector (SEAF-40-05.0-S-10-2-A-K-TR) that is an excellent choice for high numbers of differential pairs operating up to 28Gbps. A common pinout for the connector across a family of EVMs has been established. At present, the interface between the EVMs and the TSW1418EVM has defined connections for:

• 21 differential LVDS pairs or 42 single-ended CMOS signals
• 3 data clock pairs
• 5 SPI signals
• An I²C interface
• 2 FPGA optional sample clock pairs
• 4 GPIO signals

The board has:

• Four SMA interfaces to the FPGA
• A push-button hardware reset switch
• Several spare test points routed to the FPGA
• Five status LEDs

The firmware in the FPGA on the TSW1418EVM is designed to accommodate any of TI's non JESD204B/C FMC based ADCs operating in either CMOS or LVDS mode, at up to 18 bits.

The GUI loads the FPGA with the appropriate firmware based on the ADC device selected in the device drop down window. Each ADC device that appears in this window has an initialization file (.ini) associated. This .ini file contains information, such as number of channels, maximum sample rate, output interface type, number of bits, and other parameters. This information is loaded into the FPGA registers after the user clicks on the capture button. After the parameters are loaded, valid data are then captured into the FPGA internal memory. See section 2.3, Device ini Files, in the High-Speed Data Capture Pro GUI Software User's Guide for more information. Several .ini files are available to allow the user to load predetermined ADC interfaces. For example, if the user selects the ADC named ADC3683_2w_18bit, the FPGA is configured to capture data from the ADC3683EVM with the ADC interface configured for bit wise DDR mode, 18-bit LVDS, 2 converters, with a max data rate of 65 MHz.

The TSW1418EVM can capture up to 64K, 16-bit samples at a maximum data rate of 950Mbps that are stored inside the FPGA internal memory. To acquire data on a host PC, the FPGA reads the data from memory and transmits parallel data to the onboard, high-speed parallel-to-USB converter.