SLAU833A May   2020  – October 2020 ADC12DJ3200

 

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7.1 Configure the ADC EVM

Use the following steps to configure the ADC EVM.

  1. Open ADC12DJ3200EVM-CVAL GUI, choose Fclk = 3100MHz and select JMODE0 (equivalent to 6.2 GSPS ADC sample rate and 12.4Gbps lane rate) in the EVM tab.
  2. Click “Program Clocks and ADC”. On the ADC EVM, verify PLL1 LCKD LED turns on. This will indicate the LMK04828 PLL1 is locked to the onboard 100-MHz VCXO.
  3. Figure 7-1 illustrates the GUI.
    GUID-B26EE192-69FE-4CF9-ADAC-DDC4AA27CE4F-low.pngFigure 7-1 ADC12DJ3200EVM-CVAL GUI
  4. By default, the FMC+ interface EEPROM on the ADC12DJ3200EVM is installed and programmed. Please go to section 7.2.1. If using a board without this EEPROM, do the folowing steps:
  5. Go to the Low Level View tab.
  6. In the Block box near the bottom of the page, click the drop-down arrow and select "ADC12DJxx00".
  7. In the Address box enter "213”, in the Write Data box write “00”, then click the Write Register button.
  8. Click the Read Register button to verify address 0x213 is now set to 0x00, as Figure 7-2 shows.
GUID-050C1243-6517-48FE-B589-8E32E6744EDA-low.pngFigure 7-2 Low Level View Tab