SLAU833A May   2020  – October 2020 ADC12DJ3200

 

  1.   1
  2.   2
  3.   3
  4.   4
    1.     5
    2.     6
    3.     7
  5.   8
    1.     9
      1.      10
    2.     11
  6.   12
  7.   13
    1.     14
    2.     15
      1.      16
    3.     17
  8.   18

3 Functionality

The AlphaData SDEV has a standard FMC+ connector that provides an interface between this board and the TI JESD204B ADC12DJ3200CEVMCVAL. For communicating, the AlphaData SDEV uses JTAG to acquire and receive data using a host PC. The industry-standard JTAG connector is used for configuring the FPGA using the Vivado® Design Suite, a design tool by Xilinx. The firmware designed for this integration only supports JMODE0 at 6.2 GSPS single ADC. Future firmware will support all modes of this ADC.